This invention relates to memory circuits and, more particularly, to the circuit arrangement of a basic cell of a static random-access-memory (SRAM) configuration.
The basic cell of one widely used conventional SRAM consists of six transistors including four standard n-channel metal-oxide-semiconductor (MOS) transistors formed in a crystalline silicon substrate. Two of these n-channel units in each cell function as access transistors, while the other two n-channel units operate as so-called pull-down transistors, as is well known in the art. (See, for example, the cell described on pages 310-311 of MOS ICs by H. J. M. Veendrick, VCH Publishers Inc., New York, 1992.)
The aforedescribed standard six-transistor SRAM cell further includes two load devices each comprising a p-channel transistor. In high-density versions of such a cell, the p-channel devices typically comprise thin-film transistors (TFTs) formed in polysilicon on top of the aforementioned n-channel transistors. Cells including p-channel TFTs are well known in the art. Each such TFT is connected to an associated pull-down transistor of the opposite conductivity type to form an inverter. In turn, the inverters are cross-connected in a standard way to form a flip-flop. During a write operation, the condition of the state stored in the flip-flop is changed by applying electrical signals to the cross-connected inverters via the access transistors. During a read operation, the access transistors are activated and the stored contents of the flip-flop are sensed.
To ensure high-speed operation, the access and pull-down transistors of such a conventional six-transistor SRAM cell have invariably been designed to be n-channel units. Consequently, the associated load or TFT transistors have invariably been p-channel units. Heretofore, all known SRAM cells of the basic type described above have thus included six transistors comprising two p-channel TFTs and four conventional n-channel devices.
To achieve a sufficiently high ON/OFF current ratio in the inherently leaky p-channel TFTs of such a basic cell, it has been found necessary in practice to resort to special measures. Thus, for example, the p-channel units are typically made as lightly-doped-drain (LDD) structures. For a description of a typical such LDD structure as applied to the TFTs of an SRAM cell, see "High Reliability and High Performance 0.35 .mu.m Gate-Inverted TFTs for 16 Mbit SRAM Applications Using Self-Aligned LDD Structures" by C. Liu et al, IEDM 92, pages 823-826.
Another problem present in a conventional SRAM cell structure of the type described above stems from the presence therein of sodium ions. Even in a carefully controlled manufacturing process, some sodium ions inevitably end up in the structure and deleteriously affect the yield of the process, as is well known in the semiconductor art. The presence of such ions can cause excessive electrical leakage in the structure and thus degrade the performance of the cell. This degradation due to leakage stemming from the presence of sodium ions is particularly severe in the conventional n-channel transistors of the basic six-transistor cell.
Furthermore, in a conventional SRAM cell of the type specified above, the n-channel access and pull-down transistor structures typically suffer from what is commonly referred to as hot-carrier aging. This stems from the fact that in an n-type MOS transistor structure some high-kinetic-energy carriers (electrons) can penetrate into the gate oxide of the structure. (The liklihood of such penetration increases as the channel length of the transistor decreases.) In turn, such penetration can shift the threshold voltage of the transistor in an unacceptable way and cause harmful leakage in the device. In time, due to the hot-carrier-aging phenomenon, the performance of the SRAM cell may accordingly fall outside specified limits and thereby render the SRAM unsuitable for its intended function.
Thus, it was recognized that a need existed for an SRAM cell design that was simpler and less susceptible to the aforementioned sodium-ion and hot-carrier-aging phenomena. It was apparent that such a cell design, if available, could improve the yield and lower the cost of SRAMs while at the same time improving the lifetime and operating reliability of such memories.